The features which make electronics a wonderful medium for performing computations also make electronics a poor choice for massive high performance communication networks between and within computers. Despite this, a large number of parallel computer architectures, based on electronics, have been proposed and many have been built. They are summarized in the book by G. Lerman and L. Rudolph, Parallel Evolution of Parallel Processors, Plenum Press, New York, 1993, which book is incorporated herein by reference.
Currently, most of the commercial parallel supercomputers consist of a multiplicity of high performance processors which communicate via a multi-stage interconnection network. Each processor communicates with the interconnection network via its own specially designed processor-network interface.
The individual processors execute operations in excess of 100 million instructions per second (MIPS), have a local memory in excess of 64 Mbytes and can transmit messages at a rate of tens of Mbytes/second. Modern parallel supercomputers, such as the CM-5 manufactured by Thinking Machines Inc. of Cambridge, Mass., USA, the SP-1 manufactured by International Business Machines Inc. of the USA, the CS-2 manufactured by Meiko of England, the Paragon manufactured by Intel Corporation of the USA and the T3D manufactured by Cray Research Corporation of Maynard, Minn., provide the programmer with the ability to send a message between any pair of processors even if a direct link does not exist between the two processors. Each processor is typically known as a "node".
Since electronic interconnection networks cannot support full interconnectivity (i.e. each processor being directly connected to every other processor), they typically resort to multistaged networks, as described in the book by G. Almasi and A. Gottlieb, Highly Parallel Computing, Benjamin-Cummings, 1989, which book is incorporated herein by reference. Unfortunately, in many communication patterns, there are not enough links and therefore, a plurality of messages must use the same communication links. Since at most one message may traverse a link at any time, serious performance degradations can ensue. Moreover, the latency (i.e. the time needed for a message to traverse the interconnection network) increases with the size of the network. At the present time, electronic networks appear to be limited to 500 nodes.
As a result of these drawbacks, optical interconnection networks, supporting thousands of nodes, have been proposed. Some mimic the multistage networks of electronic interconnection networks and, although the optical networks may be faster, they have the same limitations as the electronic ones. Others try to mimic a bus interconnection arrangement; however, this arrangement does not scale easily. Still others route the signals through the network via a central device which, when it is modifying one connection, cannot be utilized for any other task. Finally, there are schemes based on bulk optics which require precise alignment of the optics. Almost all of the designs are on paper only and none of them are appropriate for massively parallel processing in which there are 10,000 or more processors. Furthermore, all of the prior art designs suffer from indeterminant transnission times.